As is known, demands of consolidating functions and applications from printed circuit board to a single chip are growing stronger. These demands have made the scales and designs of an Integrated Circuit (IC) increasingly complex and time consuming. For this reason, Computer-Aided Design (CAD) has become a useful tool to speed up and improve the quality of IC design. In particular, physical layout takes up a major portion of the cycle of designing an Application Specific Integrated Circuit (ASIC).
In creating a physical layout of an ASIC, a computer layout may be first generated generally by arranging a number of individual blocks or “logic cells” based on designated schematics. The functionality and design of individual logic cells may be predetermined and stored on a computer system as a standardized cell design. Such cell design techniques can save time in design cycle, as it may be no longer necessary for an IC designer to custom design each individual gate and transistor in an IC. Rather, the circuit designer breaks down a new circuit design into a number of known (or new) cell designs and then combines these cells appropriately to generate a circuit layout that performs a desired function. Each of the logic cells contains a number of terminals for implementing into the IC. To release the layout to make a mask for semiconductor processing, the data is loaded onto a tape, and is given to a mask shop, the so-called tape-out phase. To tape-out such a computer layout, commercial place-and-route CAD tools are used. More particularly, place-and-route CAD programs are used to arrange logic cells and other elements to optimize their interconnections and the overall size and to define the routing region and to select channels to connect the logic cells and elements.
A place-and-route CAD tool uses as an input a predetermined number of predefined logic cell types (e.g., Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, de-coupling capacitor, etc.) to implement the tasks mentioned above. In response, the place-and-route CAD tool outputs a computer layout. Using the computer layout generated as a blueprint, a number of basic CMOS transistor layers, contact, and metal layers defining the elements and interconnections of the IC are created in silicon through a combination of semiconductor processes, namely depositing, masking, and etching. When combined, these layers form the IC with functions.
Depending on the complexity of the ASIC, each circuit may involve multiple basic layers, multiple contacts, and multiple metal layers. This layer-pattern-release procedure is widely known as tape-out. Following tape-out, for various reasons including design changes, modifications are subsequently used to delete as well as add logic elements and interconnections from the original design. When this occurs, an engineering change order (ECO) is generated to document the desired changes. Next, the earlier generated computer layout is modified using the commercial place-and-route CAD tool to incorporate the desired changes.
Under typical methods, extra logic cells, spare or mask-programmable filler cells, of different types are included in the original computer layout as reserves in case new elements are needed. However, due to limitations inherent in the software environment, the place-and-route CAD limits uses that these extra logic cells to predefined types and numbers. For that reason, the spare cells mix and placement have to be defined at a compile step of the IC design, namely before the tape-out, thus reducing the margins for new changes. Because the types of the logic cells are predefined as Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, de-coupling capacitor, etc., modifications are limited to changing the logic cells connectivity. Such inflexibility may be undesirable.
For instance, in adding logic elements as used under an ECO, a logic cell of a certain type may not be available for implementing a desired function. As a result, either the desired function may be deleted or the process of generating a computer layout with the desired logic cells may be restarted and, of course, neither one of these options is desirable.
In addition, even if the right type logic cells are available for adding, the layout engineer may still make the proper connections, but, because the locations of the logic cells are fixed, it is sometimes not possible to provide the desired connections given existing obstacles and various space constraints in the layout. Moreover, it is a painful and time-consuming task to identify the extra logic cells and provide the proper wiring to properly connect the added cells. Because of the increasing complexity of the IC design and modification, the turn-around time to incorporate the desired ECO changes is generally high.
In addition, within the design community, a design style using a typical SoC which uses mask-programmable base cells, called ECO base cells, to replace spare cells approach for ECO implementation is also known. Such an approach allows the implementation of extra logic devoted to an error fix or ECO in a later phase of the ASIC implementation flow, thus saving design time and cost.
Recently, some mask-programmable technologies have appeared on the market with the aim to avoid the early definition of spare cells functionality in the implementation flow and to enable late changes by way of metal masks. Nevertheless, such methods are inefficient in terms of area, and in terms of performance for the implementation of debug infrastructures.
An approach which implements a simplified design technique into a device layout design through a flexible ECO base cell is described in the U.S. Patent Application Publication No. 2005/0235240 to Tien. This patent application discloses a method for reducing layer revisions in the ECO through a symmetrical ECO base cell having an N-well and a P-well, P+ implant and N+ implant regions, N-well pick-up and P-well pick-up regions, a first power supply line, and a second power supply line. This ECO base cell has a same configuration as a standard logic cell and is alterable in at least one metal layer of the chip for making one or more connections to form a functional logic cell, like Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, de-coupling capacitors, etc.
Moreover, according to the method described in this document, after placing one or more standard logic cells in the layout design according to at least one preliminary design file, one or more ECO base cells are further placed in one or more spare regions. The so placed standard logic cells are routed according to the preliminary design file. Then, at least one metal layer of at least one of the ECO base cells is altered to form the functional cell if such functional cell is needed and the placed standard logic cells are rerouted to be integrated with the thus formed functional cell.
In fact, in an original design, one or more logic cells (i.e. ECO base cells already configured as functional cells) may be placed and connected through routing to form higher level functions, and one or more base cells (i.e. ECO base cells not yet configured or virgin cells) may also be placed in predetermined locations as fillers already prepared for future revision need.
In particular, during a following design revision, the base cells can be transformed into logic or target cells through metal to silicon contacts, metal to polysilicon contacts, or other metal layer changes. Even if this approach has some advantages, it has the drawback of allowing logic changes only by mask modifications. In fact, new logic functions can be implemented exploiting the filler cell area but it can only be programmed by way of metal to silicon contacts, metal to polysilicon contacts, and metal masks. Moreover, the cell topology and granularity obtained are not optimized for a hardware debug logic implementation.
In particular, this approach with less than optimal cell topology and granularity, causes an area increase of the logic cells, increasing the routing resources needed in the ECO implementation, this being a problem for design development. As a consequence, the method described above is not efficient in terms of costs and is time consuming.
It is also known that, in spite of huge efforts in design verification, errors are still found in about two thirds of newly manufactured SoCs. The most recently developed devices however have short market windows, and the delays caused by inefficient and unpredictable debugging significantly increase the time-to-market of such devices, and thus result in a significant loss of market share, or even a complete loss of revenue.
The most commonly used tools for silicon debugging are debuggers for embedded software, but these tools provide only limited observation into the SoC hardware domain, mostly by monitoring processor busses. Most in-house techniques thus rely on ad-hoc Design for Debug (DfD) structures added to the design to provide some internal observation. However, the DfD structures are design-specific, there are no automatic tools to insert them or process the information they provide, and in general, there is little reuse from project to project. Moreover, the software used to configure and operate custom instrumentation is often inadequate. Manual instrumentation of thousands of signals takes a long time, is error-prone, and cannot easily accommodate subsequent design changes. In essence, ad-hoc methods do not scale well for future designs.
A known approach that creates DfD structures in an existing silicon layout is described in the article entitled “A Re-configurable Design-for-Debug Infrastructure for SoCs” published by DAFCA, Inc., Proc. 43rd IEEE Design Automation Conference 16, pp 7-12, July 24-28, 16. This article discloses a re-configurable logic, called “distributed re-configurable fabric”, whose components are DfD structures that can be widely distributed on a silicon layout and that are generated on-the-fly for a target SoC. Moreover, the models of the generated instruments are automatically inserted in the Register Transfer Language (RTL) model of such a SoC and the instrumented RTL design goes through the normal synthesis and physical design flow.
The SoC with DfD structures described in this article comprise several types of re-configurable instruments, such as: a Signal Probe Network (SPN) that is a multiplexer (MUX) network that collects a group of signals and selects a subgroup of them to be brought to processing instruments; a Debug Monitor (DEMON) that analyzes a group of signals; a Wrapper that has signal analysis features; a Tracer that contains a buffer memory that can record inputs signals; a CapStim that is a Tracer whose memory may be preloaded with vectors; a Serial Access Node (SAN) to prepare data for communication with an external world; and a Primary CONtroller (PCON) to manage communication with the external world.
This software re-configurable DfD infrastructure logic allows observation and control of some internal signals of the SoC and thanks to its reconfiguration capability, it is also possible to implement functional changes on the final device, after receiving silicon back from the semiconductor process, without resorting to costly ECO techniques. ECO mask changes are needed only if the software re-configurable DfD infrastructure cannot be used to fix errors or to implement the requested functional changes.
The debug structures or tools reside in a workstation connected to the target SoC via a JTAG (acronym of “Joint Test Action Group”) cable. They configure and operate the debug instruments using only the standard JTAG pins and the JTAG clock. Even if the described approach is advantageous for several aspects, it has the drawback that a new product revision is needed in order to change the used debug structures.